摘 要
隨著網⊙絡的普及和發展，對數據的傳輸標準也在隨之不斷的提高。這就在數據的控制問題上提出了〖更大的要求。在數字信號中，數據一般都是以幀結】構存在的，各個時隙的位置可以根據幀定界信號加以識別。因此在數字通信網中，幀同步︾是同步復接中最重要的部分，它包括幀同步碼的產生和幀同步碼的識別。
文中介◤紹了二分查找法的工作原理及幀同步的實現過程。在研究運算規則的▆同時,根據國際光互聯論壇制定的甚短距離光傳輸標準對三種不同的查找方案進行ㄨ了比較,最終選擇二分查找法作為實踐對象。其中，基本結構設計上采♂用了六級並行計算模式，再根據具體步驟制定幀同步的流程圖，並以Altera公→司開發的EDA工具QuartusII作為編譯、仿真平臺，完成了幀同步的硬件語言描述，從而達到了對數據結構中幀定界的查找目的。通過對仿真測試和對輸出波形的理論分析，證明程序工作正常、方法行之有效，可以滿足相◥關標準及使用要求，並在速度、準確率體現了二分查找算法的優越性。
關鍵字：幀定界；幀同步碼；FPGA；甚短距離光傳輸
ABSTRACT
Along with the universality and developments of the network, the data’s delivering standards was also in the immediately continuous exaltation. This put forward the greater request on the control problem of the data. In digital signal, the data invariably existed with the structure of framer, and the each position of the time partition could be located with framer Delimitation. Therefore, in the digital connecting system, the framer’s synchronization was the most important part, and it included the creation and identification of the framer’s synchronization code.
The essay introduces working principle of the seeking law and the realization of frame synchronization. When research operation is regular, with the standard of very short reach which is made by optical international forum to compare the three different seeking schemes, eventually select the dividing-seeking is practice object. In which, on basic structural design has adopted 6 level parallel calculations pattern, establish the flow chart of frame synchronization again according to specific step, and with the EDA tool of Altera company's development Quartus II action compile and emulate platform, have completed the hardware language of framer synchronization describe, so have reached the delimiter seeking purpose in data structure. Through the emulation test and the theoretical analysis for export waveform, proof program work is normal , has effective method , can satisfy relative standard and use to ask , and has embodied the voluntarily optimize function in the process.
Key words: framer Delimitation；the framer’s synchronization code；FPGA；VSR
目 錄
1 緒論 1
1.1 SDH與幀同步概述 1
1.2 FPGA現狀與發展 2
1.3 論文內容介紹← 3
2 幀同步 4
2.1 引言 4
2.2 幀數據結構 4
2.3數據傳送 5
2.3.1 發送方向的數據傳送 5
2.3.2 接收方向的數據傳送 5
2.3.3 OC-192幀至數據通道映射 5
2.4 VSR幀同步 6
3 算法原理 8
3.1 引言 8
3.2 OC-192幀同步模塊功能描述 8
3.3 幀對齊方案 8
3.3.1 常見幀對齊方案概要 8
3.3.2 幀對齊電路結構性能分析 12
3.3.3 OC-192幀同步模塊總體電路結構 12
4 設計與實現 13
4.1研究背∮景與語言工具簡介 13
4.1.1 FPGA概述 13
4.1.2 Verilog HDL語言簡介 13
4.1.3 Quartus II仿真環境簡介 14
4.2 幀同步算法的設計 16
4.2.1 模塊設計 17
4.2.2 設計仿真 23
5 結論 26
6 參考文獻 27
7 附錄 28
7.1 基於Verilog HDL語言的實體整體描〓述 28
7.2 二分查找法原理仿真圖 34
8 致謝 35
